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-rw-r--r--src/core/CMakeLists.txt2
-rw-r--r--src/core/arm/dyncom/arm_dyncom.cpp5
-rw-r--r--src/core/arm/dyncom/arm_dyncom_thumb.cpp6
-rw-r--r--src/core/arm/skyeye_common/armdefs.h4
-rw-r--r--src/core/arm/skyeye_common/armos.h54
-rw-r--r--src/core/arm/skyeye_common/skyeye_defs.h13
6 files changed, 2 insertions, 82 deletions
diff --git a/src/core/CMakeLists.txt b/src/core/CMakeLists.txt
index fa6b4215a..aaa6d87f3 100644
--- a/src/core/CMakeLists.txt
+++ b/src/core/CMakeLists.txt
@@ -115,8 +115,6 @@ set(HEADERS
arm/skyeye_common/armdefs.h
arm/skyeye_common/armemu.h
arm/skyeye_common/armmmu.h
- arm/skyeye_common/armos.h
- arm/skyeye_common/skyeye_defs.h
arm/skyeye_common/vfp/asm_vfp.h
arm/skyeye_common/vfp/vfp.h
arm/skyeye_common/vfp/vfp_helper.h
diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp
index 42a63e46f..0072ae533 100644
--- a/src/core/arm/dyncom/arm_dyncom.cpp
+++ b/src/core/arm/dyncom/arm_dyncom.cpp
@@ -16,10 +16,6 @@
#include "core/core.h"
#include "core/core_timing.h"
-const static cpu_config_t s_arm11_cpu_info = {
- "armv6", "arm11", 0x0007b000, 0x0007f000, NONCACHE
-};
-
ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
state = Common::make_unique<ARMul_State>();
@@ -27,7 +23,6 @@ ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
ARMul_SelectProcessor(state.get(), ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
state->abort_model = ABORT_BASE_RESTORED;
- state->cpu = (cpu_config_t*)&s_arm11_cpu_info;
state->bigendSig = LOW;
state->lateabtSig = LOW;
diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.cpp b/src/core/arm/dyncom/arm_dyncom_thumb.cpp
index bfb45f104..08b5c0b77 100644
--- a/src/core/arm/dyncom/arm_dyncom_thumb.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_thumb.cpp
@@ -6,8 +6,6 @@
// ARM instruction, and using the existing ARM simulator.
#include "core/arm/dyncom/arm_dyncom_thumb.h"
-#include "core/arm/skyeye_common/armos.h"
-#include "core/arm/skyeye_common/skyeye_defs.h"
// Decode a 16bit Thumb instruction. The instruction is in the low 16-bits of the tinstr field,
// with the following Thumb instruction held in the high 16-bits. Passing in two Thumb instructions
@@ -288,7 +286,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
: 0xE28DDF00) // ADD
|(tinstr & 0x007F); // off7
} else if ((tinstr & 0x0F00) == 0x0e00)
- *ainstr = 0xEF000000 | SWI_Breakpoint;
+ *ainstr = 0xEF000000 | 0x180000; // base | BKPT mask
else {
static const ARMword subset[4] = {
0xE92D0000, // STMDB sp!,{rlist}
@@ -320,7 +318,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
*ainstr |= ((tinstr & 0x00FF) << 16);
// New breakpoint value. See gdb/arm-tdep.c
else if ((tinstr & 0x00FF) == 0xFE)
- *ainstr |= SWI_Breakpoint;
+ *ainstr |= 0x180000; // base |= BKPT mask
else
*ainstr |= (tinstr & 0x00FF);
} else if ((tinstr & 0x0F00) != 0x0E00)
diff --git a/src/core/arm/skyeye_common/armdefs.h b/src/core/arm/skyeye_common/armdefs.h
index 85d523bc2..470f9508d 100644
--- a/src/core/arm/skyeye_common/armdefs.h
+++ b/src/core/arm/skyeye_common/armdefs.h
@@ -21,7 +21,6 @@
#include "common/common_types.h"
#include "core/arm/skyeye_common/arm_regformat.h"
-#include "core/arm/skyeye_common/skyeye_defs.h"
#define BITS(s, a, b) ((s << ((sizeof(s) * 8 - 1) - b)) >> (sizeof(s) * 8 - b + a - 1))
#define BIT(s, n) ((s >> (n)) & 1)
@@ -152,9 +151,6 @@ So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
// 0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model
int abort_model;
- // Added by ksh in 2005-10-1
- cpu_config_t* cpu;
-
// TODO(bunnei): Move this cache to a better place - it should be per codeset (likely per
// process for our purposes), not per ARMul_State (which tracks CPU core state).
std::unordered_map<u32, int> instruction_cache;
diff --git a/src/core/arm/skyeye_common/armos.h b/src/core/arm/skyeye_common/armos.h
deleted file mode 100644
index 1217a728b..000000000
--- a/src/core/arm/skyeye_common/armos.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* armos.h -- ARMulator OS definitions: ARM6 Instruction Emulator.
- Copyright (C) 1994 Advanced RISC Machines Ltd.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-*/
-
-//
-// SWI Numbers
-//
-
-#define SWI_Syscall 0x0
-#define SWI_Exit 0x1
-#define SWI_Read 0x3
-#define SWI_Write 0x4
-#define SWI_Open 0x5
-#define SWI_Close 0x6
-#define SWI_Seek 0x13
-#define SWI_Rename 0x26
-#define SWI_Break 0x11
-
-#define SWI_Times 0x2b
-#define SWI_Brk 0x2d
-
-#define SWI_Mmap 0x5a
-#define SWI_Munmap 0x5b
-#define SWI_Mmap2 0xc0
-
-#define SWI_GetUID32 0xc7
-#define SWI_GetGID32 0xc8
-#define SWI_GetEUID32 0xc9
-#define SWI_GetEGID32 0xca
-
-#define SWI_ExitGroup 0xf8
-
-#define SWI_Uname 0x7a
-#define SWI_Fcntl 0xdd
-#define SWI_Fstat64 0xc5
-#define SWI_Gettimeofday 0x4e
-#define SWI_Set_tls 0xf0005
-
-#define SWI_Breakpoint 0x180000 /* see gdb's tm-arm.h */
-
diff --git a/src/core/arm/skyeye_common/skyeye_defs.h b/src/core/arm/skyeye_common/skyeye_defs.h
deleted file mode 100644
index 94b02459d..000000000
--- a/src/core/arm/skyeye_common/skyeye_defs.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#pragma once
-
-#include "common/common_types.h"
-
-struct cpu_config_t
-{
- const char* cpu_arch_name; // CPU architecture version name.e.g. ARMv4T
- const char* cpu_name; // CPU name. e.g. ARM7TDMI or ARM720T
- u32 cpu_val; // CPU value; also call MMU ID or processor id;see
- // ARM Architecture Reference Manual B2-6
- u32 cpu_mask; // cpu_val's mask.
- u32 cachetype; // CPU cache type
-};
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