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2014-08-06GSP: Implements preliminary command synchronization via GPU interrupts.bunnei1-8/+12
2014-06-13HLE: Updated all uses of NULL to nullptr (to be C++11 compliant)bunnei1-4/+4
2014-06-13Core: Cleaned up SingleStep(), updated default LCD refresh to assume each instruction is ~3 cyclesbunnei1-11/+12
2014-06-13Core: Changed HW update/thread reschedule to occur more frequently (assume each instruction is ~3 cycles)bunnei1-2/+2
2014-06-05hle: added a hokey way to force a thread reschedule during CPU single step mode (as used by the debugger)bunnei1-1/+2
2014-05-30core: changed time delay before kernel reschedule to "approximate" a screen refreshbunnei1-3/+12
2014-05-23core: added Kernel::Reschedule() call to check for thread changes, shortened delay time to 100 instructionsbunnei1-1/+6
2014-05-17updated how we call ARM core to make things much fasterbunnei1-3/+6
2014-04-11cleaned up some logging messagesbunnei1-20/+2
2014-04-11added initial modules for setting up SysCall HLEbunnei1-0/+18
2014-04-09fixed project includes to use new directory structurebunnei1-6/+8
2014-04-09got rid of 'src' folders in each sub-projectbunnei1-0/+0
2014-04-09fixed some license headers that I missedbunnei1-23/+3
2014-04-05added g_app_core->Step and HW::Update to Core::SingleStep to be consistent with other changes madebunnei1-1/+5
2014-04-05- added an interface layer for ARM coresbunnei1-76/+11
2014-04-04added some commented out ARMulator functionsbunnei1-20/+3
2014-04-04Add Core::GetState() for debuggerMathieu Vaillancourt1-0/+5
2014-04-01added very hackish ARMulator core initialization and CPU steppingbunnei1-6/+97
2013-10-03moved some core functions over to system moduleShizZy1-4/+2
2013-10-02added a message option to Core::Halt functionShizZy1-1/+1
2013-09-27added system.h to projectShizZy1-3/+15
2013-09-19added log msg to coreShizZy1-0/+2
2013-09-14renamed project to 'citrus'ShizZy1-1/+1
2013-09-08updated common pathsShizZy1-0/+2
2013-09-06added core and mem_map files to the projectShizZy1-2/+46
2013-09-05added missing filesShizZy1-0/+2
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