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authorbunnei <ericbunnie@gmail.com>2014-06-14 18:13:16 +0200
committerbunnei <ericbunnie@gmail.com>2014-06-14 18:13:16 +0200
commit004df767953a949817da89bddcd5d1379240f769 (patch)
treeb2d54928dcbf3cb4dde0cd5d3277afe7999b7bd9 /src/core/arm/interpreter
parentGPU debugger: Const correctness and build fix. (diff)
parentKernel: Removed unnecessary "#pragma once". (diff)
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Diffstat (limited to 'src/core/arm/interpreter')
-rw-r--r--src/core/arm/interpreter/arm_interpreter.cpp14
-rw-r--r--src/core/arm/interpreter/arm_interpreter.h3
-rw-r--r--src/core/arm/interpreter/armemu.cpp18
3 files changed, 15 insertions, 20 deletions
diff --git a/src/core/arm/interpreter/arm_interpreter.cpp b/src/core/arm/interpreter/arm_interpreter.cpp
index 17f787b86..0e893f182 100644
--- a/src/core/arm/interpreter/arm_interpreter.cpp
+++ b/src/core/arm/interpreter/arm_interpreter.cpp
@@ -98,7 +98,7 @@ u64 ARM_Interpreter::GetTicks() const {
* @param num_instructions Number of instructions to executes
*/
void ARM_Interpreter::ExecuteInstructions(int num_instructions) {
- state->NumInstrsToExecute = num_instructions;
+ state->NumInstrsToExecute = num_instructions - 1;
ARMul_Emulate32(state);
}
@@ -118,6 +118,9 @@ void ARM_Interpreter::SaveContext(ThreadContext& ctx) {
ctx.fpscr = state->VFP[1];
ctx.fpexc = state->VFP[2];
+
+ ctx.reg_15 = state->Reg[15];
+ ctx.mode = state->NextInstr;
}
/**
@@ -137,6 +140,11 @@ void ARM_Interpreter::LoadContext(const ThreadContext& ctx) {
state->VFP[1] = ctx.fpscr;
state->VFP[2] = ctx.fpexc;
- state->Reg[15] = ctx.pc;
- state->NextInstr = RESUME;
+ state->Reg[15] = ctx.reg_15;
+ state->NextInstr = ctx.mode;
+}
+
+/// Prepare core for thread reschedule (if needed to correctly handle state)
+void ARM_Interpreter::PrepareReschedule() {
+ state->NumInstrsToExecute = 0;
}
diff --git a/src/core/arm/interpreter/arm_interpreter.h b/src/core/arm/interpreter/arm_interpreter.h
index 6a531e497..1e82883a2 100644
--- a/src/core/arm/interpreter/arm_interpreter.h
+++ b/src/core/arm/interpreter/arm_interpreter.h
@@ -72,6 +72,9 @@ public:
*/
void LoadContext(const ThreadContext& ctx);
+ /// Prepare core for thread reschedule (if needed to correctly handle state)
+ void PrepareReschedule();
+
protected:
/**
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index e5dc7bd44..f3c14e608 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -4456,6 +4456,7 @@ ARMul_Emulate26 (ARMul_State * state)
}
/* Drop through. */
+ case 0xe0:
case 0xe4:
case 0xe6:
case 0xe8:
@@ -4489,7 +4490,6 @@ ARMul_Emulate26 (ARMul_State * state)
/* Co-Processor Register Transfers (MRC) and Data Ops. */
- case 0xe0:
case 0xe1:
case 0xe3:
case 0xe5:
@@ -4533,23 +4533,7 @@ ARMul_Emulate26 (ARMul_State * state)
case 0xfd:
case 0xfe:
case 0xff:
- if (instr == ARMul_ABORTWORD
- && state->AbortAddr == pc) {
- /* A prefetch abort. */
- XScale_set_fsr_far (state,
- ARMul_CP15_R5_MMU_EXCPT,
- pc);
- ARMul_Abort (state,
- ARMul_PrefetchAbortV);
- break;
- }
- //sky_pref_t* pref = get_skyeye_pref();
- //if(pref->user_mode_sim){
- // ARMul_OSHandleSWI (state, BITS (0, 23));
- // break;
- //}
HLE::CallSVC(instr);
- ARMul_Abort (state, ARMul_SWIV);
break;
}
}