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| author | lat9nq <22451773+lat9nq@users.noreply.github.com> | 2021-07-12 04:10:38 +0200 |
|---|---|---|
| committer | ameerj <52414509+ameerj@users.noreply.github.com> | 2021-07-23 03:51:40 +0200 |
| commit | 49946cf780c317b4c5ccabb52ec433eba01c1970 (patch) | |
| tree | 628060b15b133cf3a1aaf716fba3517fc5c983f0 /src/shader_recompiler/backend/spirv/emit_spirv_image.cpp | |
| parent | main: Update Shader Cache menu options (diff) | |
| download | yuzu-49946cf780c317b4c5ccabb52ec433eba01c1970.tar yuzu-49946cf780c317b4c5ccabb52ec433eba01c1970.tar.gz yuzu-49946cf780c317b4c5ccabb52ec433eba01c1970.tar.bz2 yuzu-49946cf780c317b4c5ccabb52ec433eba01c1970.tar.lz yuzu-49946cf780c317b4c5ccabb52ec433eba01c1970.tar.xz yuzu-49946cf780c317b4c5ccabb52ec433eba01c1970.tar.zst yuzu-49946cf780c317b4c5ccabb52ec433eba01c1970.zip | |
Diffstat (limited to 'src/shader_recompiler/backend/spirv/emit_spirv_image.cpp')
| -rw-r--r-- | src/shader_recompiler/backend/spirv/emit_spirv_image.cpp | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp index 647804814..3588f052b 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp +++ b/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp @@ -109,7 +109,7 @@ private: return; } if (offset.IsImmediate()) { - Add(spv::ImageOperandsMask::ConstOffset, ctx.SConst(offset.U32())); + Add(spv::ImageOperandsMask::ConstOffset, ctx.SConst(static_cast<s32>(offset.U32()))); return; } IR::Inst* const inst{offset.InstRecursive()}; @@ -117,16 +117,21 @@ private: switch (inst->GetOpcode()) { case IR::Opcode::CompositeConstructU32x2: Add(spv::ImageOperandsMask::ConstOffset, - ctx.SConst(inst->Arg(0).U32(), inst->Arg(1).U32())); + ctx.SConst(static_cast<s32>(inst->Arg(0).U32()), + static_cast<s32>(inst->Arg(1).U32()))); return; case IR::Opcode::CompositeConstructU32x3: Add(spv::ImageOperandsMask::ConstOffset, - ctx.SConst(inst->Arg(0).U32(), inst->Arg(1).U32(), inst->Arg(2).U32())); + ctx.SConst(static_cast<s32>(inst->Arg(0).U32()), + static_cast<s32>(inst->Arg(1).U32()), + static_cast<s32>(inst->Arg(2).U32()))); return; case IR::Opcode::CompositeConstructU32x4: Add(spv::ImageOperandsMask::ConstOffset, - ctx.SConst(inst->Arg(0).U32(), inst->Arg(1).U32(), inst->Arg(2).U32(), - inst->Arg(3).U32())); + ctx.SConst(static_cast<s32>(inst->Arg(0).U32()), + static_cast<s32>(inst->Arg(1).U32()), + static_cast<s32>(inst->Arg(2).U32()), + static_cast<s32>(inst->Arg(3).U32()))); return; default: break; |