1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
|
// Copyright 2021 yuzu Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include <string>
#include <string_view>
#include <fmt/format.h>
#include "shader_recompiler/backend/glsl/reg_alloc.h"
#include "shader_recompiler/exception.h"
#include "shader_recompiler/frontend/ir/value.h"
namespace Shader::Backend::GLSL {
namespace {
std::string Representation(Id id) {
if (id.is_condition_code != 0) {
throw NotImplementedException("Condition code");
}
if (id.is_spill != 0) {
throw NotImplementedException("Spilling");
}
const u32 index{static_cast<u32>(id.index)};
return fmt::format("R{}", index);
}
std::string FormatFloat(std::string_view value, IR::Type type) {
// TODO: Confirm FP64 nan/inf
if (type == IR::Type::F32) {
if (value == "nan") {
return "uintBitsToFloat(0x7fc00000)";
}
if (value == "inf") {
return "uintBitsToFloat(0x7f800000)";
}
if (value == "-inf") {
return "uintBitsToFloat(0xff800000)";
}
}
const bool needs_dot = value.find_first_of('.') == std::string_view::npos;
const bool needs_suffix = !value.ends_with('f');
const auto suffix = type == IR::Type::F32 ? "f" : "lf";
return fmt::format("{}{}{}", value, needs_dot ? "." : "", needs_suffix ? suffix : "");
}
std::string MakeImm(const IR::Value& value) {
switch (value.Type()) {
case IR::Type::U1:
return fmt::format("{}", value.U1() ? "true" : "false");
case IR::Type::U32:
return fmt::format("{}u", value.U32());
case IR::Type::F32:
return FormatFloat(fmt::format("{}", value.F32()), IR::Type::F32);
case IR::Type::U64:
return fmt::format("{}ul", value.U64());
case IR::Type::F64:
return FormatFloat(fmt::format("{}", value.F64()), IR::Type::F64);
case IR::Type::Void:
return "";
default:
throw NotImplementedException("Immediate type {}", value.Type());
}
}
} // Anonymous namespace
std::string RegAlloc::Define(IR::Inst& inst) {
const Id id{Alloc()};
inst.SetDefinition<Id>(id);
return Representation(id);
}
std::string RegAlloc::Define(IR::Inst& inst, Type type) {
const Id id{Alloc()};
std::string type_str = "";
if (!register_defined[id.index]) {
register_defined[id.index] = true;
type_str = GetGlslType(type);
}
inst.SetDefinition<Id>(id);
return type_str + Representation(id);
}
std::string RegAlloc::Define(IR::Inst& inst, IR::Type type) {
return Define(inst, RegType(type));
}
std::string RegAlloc::Consume(const IR::Value& value) {
return value.IsImmediate() ? MakeImm(value) : Consume(*value.InstRecursive());
}
std::string RegAlloc::Consume(IR::Inst& inst) {
const Id id{inst.Definition<Id>()};
inst.DestructiveRemoveUsage();
// TODO: reuse variables of same type if possible
// if (!inst.HasUses()) {
// Free(id);
// }
return Representation(inst.Definition<Id>());
}
Type RegAlloc::RegType(IR::Type type) {
switch (type) {
case IR::Type::U1:
return Type::U1;
case IR::Type::U32:
return Type::U32;
case IR::Type::F32:
return Type::F32;
case IR::Type::U64:
return Type::U64;
case IR::Type::F64:
return Type::F64;
default:
throw NotImplementedException("IR type {}", type);
}
}
std::string RegAlloc::GetGlslType(Type type) {
switch (type) {
case Type::U1:
return "bool ";
case Type::F16x2:
return "f16vec2 ";
case Type::U32:
return "uint ";
case Type::S32:
return "int ";
case Type::F32:
return "float ";
case Type::S64:
return "int64_t ";
case Type::U64:
return "uint64_t ";
case Type::F64:
return "double ";
case Type::U32x2:
return "uvec2 ";
case Type::F32x2:
return "vec2 ";
case Type::U32x4:
return "uvec4 ";
case Type::F32x4:
return "vec4 ";
case Type::Void:
return "";
default:
throw NotImplementedException("Type {}", type);
}
}
std::string RegAlloc::GetGlslType(IR::Type type) {
return GetGlslType(RegType(type));
}
Id RegAlloc::Alloc() {
if (num_used_registers < NUM_REGS) {
for (size_t reg = 0; reg < NUM_REGS; ++reg) {
if (register_use[reg]) {
continue;
}
register_use[reg] = true;
Id ret{};
ret.is_valid.Assign(1);
ret.is_long.Assign(0);
ret.is_spill.Assign(0);
ret.is_condition_code.Assign(0);
ret.index.Assign(static_cast<u32>(reg));
return ret;
}
}
throw NotImplementedException("Register spilling");
}
void RegAlloc::Free(Id id) {
if (id.is_spill != 0) {
throw NotImplementedException("Free spill");
}
register_use[id.index] = false;
}
} // namespace Shader::Backend::GLSL
|